Controller for an optical disk drive, semiconductor integrated circuit and optical disk drive

ABSTRACT

A controller for an optical disk drive includes a modulator configured to modulate a record data to be recorded on a optical disk based on a record clock that is a reference clock in recording, and to generate a modulation data and an address information of the modulation data. A prepit decoder is configured to generate a prepit clock from a prepit signal detected from the optical disk, and a decision circuit is configured to determine whether or not recording in accordance with a standard is performed, from phase characteristic based on the address information and the prepit clock, and to control a frequency of the record clock.

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application is based upon and claims the benefit of priorityfrom the prior Japanese Patent Applications No. P2002-256144, filed onAug. 30, 2002; the entire contents of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to an optical disk drive and, moreparticularly, to a controller for the optical disk drive and asemiconductor integrated circuit monolithically integrating thecontroller on a single semiconductor chip.

[0004] 2. Description of the Related Art

[0005] A compact disk-recordable/rewritable (CD-R/RW) device isavailable as a recordable optical disk. Moreover, digital versatiledisk-recordable/rewritable (DVD-RW) and digital versatiledisk+recordable/rewritable (DVD+RW) devices are available as opticaldisks, which have a large-capacity compared to the CD-R/RW. Inrecording, “additional write”, i.e., writing new data which includespreviously recorded data on the optical disk is offer necessary. Astandard has been established such that an end of the previouslyrecorded data and an initial point of new data coincide with each otherwithin an accuracy of ±1 byte.

[0006] In order to permit the additional write in accordance with thestandard, a method of recording new data on the optical disk by use ofan information signal as a reference has been proposed (hereinafterreferred to as “first background art”). The information signal isobtained from the optical disk. Also, a method of recording new data onthe optical disk based on a wobble clock obtained by multiplying awobble signal has been proposed (hereinafter referred to as “secondbackground art”).

[0007] In the first background art, when the previously recorded data onthe optical disk deviates from the standards, the new data deviates fromthe prepits and a wobble. Furthermore, in a digital versatile disk (DVD)drive and the like, a track pitch is narrower than the size of a beamspot. As a result, crosstalk often occurs between tracks. Under theinfluence of the wobble of adjacent tracks on the optical disk, thewobble signal is subjected to an amplitude modulation (AM) and afrequency modulation (FM). When the wobble signal undergoes the AM andthe FM modulation, an error occurs in the wobble clock.

[0008] Therefore, according to the second background art, it isdifficult to maintain phases of the record sync and prepits constantly,by use of the wobble clock as the reference. Furthermore, when thepreviously recorded data on the optical disk deviates from the standard,new data is recorded in accordance with prepits and the wobble, whileignoring the deviating data. If the new data is recorded while ignoringthe previously recorded deviation data, there is a possibility that thepreviously recorded data will be destroyed.

SUMMARY OF THE INVENTION

[0009] An aspect of the present invention inheres in a controller for anoptical disk drive encompassing, a modulator configured to modulaterecord data to be recorded on an optical disk based on a record clockwhich is a reference clock for recording, and to generate modulationdata and address information of the modulation data, a prepit decoderconfigured to generate a prepit clock from a prepit signal detected fromthe optical disk, and a decision circuit configured to determine whetherrecording in accordance with a standard is performed, from a phasecharacteristic based on the address information and the prepit clock,and to control a frequency of the record clock.

[0010] Another aspect of the present invention inheres in asemiconductor integrated circuit encompassing, a modulator integrated onsemiconductor chip and configured to modulate a record data to berecorded on a optical disk based on a record clock that is a referenceclock for recording, and to generate a modulation data and an addressinformation of the modulation data, a prepit decoder integrated on thesemiconductor chip and configured to generate a prepit clock from aprepit signal detected from the optical disk, and a decision circuitintegrated on the semiconductor chip and configured to determine whetheror not recording in accordance with a standard is performed, from phasecharacteristic based on the address information and the prepit clock,and to control a frequency of the record clock.

[0011] Still another aspect of the present invention inheres in anoptical disk drive encompassing, a pickup configured to read lightreflected from an optical disk, the reflected light generated byirradiating a laser beam on the optical disk, and to generate a prepitsignal and a wobble signal, a controller configured to determine whetherrecording in accordance with an established standards is performed, fromphase characteristic based on the prepit signal and the wobble signal,and to modulate record data to be recorded on the optical disk, and asignal processor configured to supply the record data to the controller.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1 is a schematic view showing configurations of lands andgrooves on an optical disk;

[0013]FIG. 2 is a schematic diagram showing a spiral configuration ofthe optical disk;

[0014]FIG. 3 is a schematic plan view showing configurations of thelands and the grooves;

[0015]FIG. 4 is a block diagram showing an optical disk drive accordingto a first embodiment of the present invention;

[0016]FIG. 5 is a block diagram showing a controller for the opticaldisk drive according to the first embodiment of the present invention;

[0017]FIGS. 6A and 6B are schematic diagrams showing a relationship of aprepit signal and a record sync in the optical disk drive according tothe first embodiment of the present invention;

[0018]FIGS. 7A and 7B are schematic diagrams showing a relationship of awobble signal and a record sync in the optical disk drive according tothe first embodiment of the present invention;

[0019] FIGS. 8A-8E are time charts showing an operation of thecontroller according to the first embodiment of the present invention;

[0020]FIG. 9 is schematic diagram showing a function of a decisioncircuit according to the first embodiment of the present invention;

[0021]FIG. 10 is a schematic diagram showing a configuration integratedthe controller according to the first embodiment of the presentinvention monolithically on the same semiconductor chip;

[0022]FIG. 11 is a schematic diagram showing a mounting example of thesemiconductor integrated circuit according to the second embodiment ofthe present invention;

[0023]FIG. 12 is a block diagram showing an optical disk drive accordingto a second embodiment of the present invention;

[0024]FIG. 13 is a block diagram showing a controller for the opticaldisk drive according to the second embodiment of the present invention;

[0025]FIGS. 14A and 14B are schematic diagram showing states of framesin a addition writing of the record controller according to the secondembodiment of the present invention;

[0026] FIGS. 15A-15F are time charts showing an operation of thecontroller according to the second embodiment of the present invention;

[0027]FIGS. 16A and 16B are schematic diagram showing a function of adecision circuit according to the second embodiment of the presentinvention;

[0028]FIG. 17 is a schematic diagram showing a configuration integratedthe controller according to the second embodiment of the presentinvention monolithically on the same semiconductor chip; and

[0029]FIG. 18 is a block diagram showing a controller for an opticaldisk drive according to other embodiments of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS

[0030] Various embodiments of the present invention will be describedwith reference to the accompanying drawings. It is to be noted that thesame or similar reference numerals are applied to the same or similarparts and elements throughout the drawings, and description of the sameor similar parts and elements will be omitted or simplified. In thefollowing descriptions, numerous specific details are set forth such asspecific signal values, etc. to provide a thorough understanding of thepresent invention. However, it will be obvious to those skilled in theart that the present invention may be practiced without such specificdetails. In other instances, well-known circuits have been shown inblock diagram form in order not to obscure the present invention withunnecessary detail. In the following description, the words “connect” or“connected” defines a state in which first and second elements areelectrically connected to each other without regard to whether or notthere is a physical connection between the elements.

[0031] As shown in FIG. 1, in order to guide a pickup that reads areflected light by irradiating a laser beam on an optical disk, aCD-R/RW, a DVD-R/RW and a DVD+R/RW have grooves 102 a, 102 b, . . . andlands 101 a, 101 b, . . . As shown in FIG. 2, the grooves 102 a, 102 b,. . . and the lands 101 a, 101 b, . . . wobble at a constant period in aradial direction of the optical disk 11, i.e., the lands and grooveshave a “wobbling” characteristic. A track structure of the optical disk11 as shown in FIGS. 1 and 2 is called a “wobbled land groove”. As shownin FIG. 3, prepits 104 a, 104 b, . . . are inscribed in the lands 101 a,101 b, . . . , particularly in the DVD-R/RW. Furthermore, pits 105 a,105 b, are formed by the laser beam irradiated from the pickup. A wobblesignal, a prepit signal and an information signal are generated from asignal read out from the optical disk 11 by the pickup. The wobblesignal is generated in accordance with the wobble shown in FIG. 2. Theprepit signal is generated in accordance with the prepits 104 a, 104 b,shown in FIG. 3.

[0032] (First Embodiment)

[0033] As shown in FIG. 4, an optical disk drive according to a firstembodiment of the present invention includes an optical disk 11, apickup configured to receive light reflected from a laser beamirradiated on the optical disk 11, and to generate a prepit signal PSand a wobble signal WS. Also included is a controller 1 a configured todetermine whether or not recording in accordance with the standards isperformed, based on phase characteristic of the prepit signal PS and thewobble signal WS, and to modulate record data RD which is to be recordedon the optical disk 11. A signal processor 3 a is provided andconfigured to supply the record data RD to the controller 1 a.Furthermore, the optical disk drive according to the first embodimentincludes a disk motor 71 configured to drive the optical disk 11, aservo controller 16 configured to control operation of the pickup 12based on an error signal ES detected by the pickup 12, a laser driver 25configured to drive a laser in the pickup 12 based on a modulation dataMD supplied from the controller 1 a, a disk motor controller 29configured to control rotation of the disk motor 71, a crystaloscillator 76 configured to supply a reference clock CLK1 to the diskmotor controller 29 and the signal processor 3 a, and a systemcontroller 31 a configured to control the entire system in accordancewith operation modes such as recording and reproducing data.

[0034] An optical detector (not illustrated) inside the pickup 12 isdivided into four sections, A to D. A radio frequency (RF) amplifier 15performs a matrix operation on each of the signals detected by therespective A to D sections, and generates the prepit signal PS, thewobble signal WS, the information signal RF and the error signal ES. Thecontroller 1 a includes a modulator 24 a configured to modulate therecord data RD based on a record clock RCLK, used as a reference clockin recording, and to generate the modulation data MD and an addressinformation AD of the modulation data MD, a prepit decoder 27 aconfigured to generate a prepit clock PCLK from the prepit signal PSdetected from the optical disk 11, and a decision circuit 33 aconfigured to determine whether or not recording in accordance with thestandard is performed from phase characteristic based on the addressinformation AD and the prepit clock PCLK, and to control a frequency ofthe record clock RCLK. The controller 1 a further includes a wobble PLL26 a configured to generate a wobble clock WCLK based on the wobblesignal WS, and a record clock generator 30 a configured to generate therecord clock RCLK.

[0035] Furthermore, as shown in FIG. 5, the modulator 24 a includes awobble counter 57 a configured to generate a sector synchronizationsignal SY by counting the wobble clock WCLK, a timing controller 58 aconfigured to generate a timing signal TS in synchronization with anyone of the sector synchronization signal SY and a reproducingsynchronization signal RP, an encode address counter 40 a configured togenerate a modulation control signal MC and the address information ADby counting the record clock RCLK when the timing signal TS iseffective, and a modulation data generator 59 a configured to modulatethe record data RD based on the modulation control signal MC. In thecase of recording new data on the optical disk 11 by use of thepreviously recorded data, that is, the information signal RF is used asa reference, the timing controller 58 a generates the timing signal TSin accordance with the reproducing synchronization signal RP. On theother hand, in the case of recording new data on the optical disk 11 byuse of the wobble clock WCLK as a reference, the timing controller 58 agenerates the timing signal TS in synchronization with the sectorsynchronization signal SY. In the DVD drive, the address information ADembedded in the modulation data MD is called “logic ID”.

[0036] The prepit decoder 27 a includes a prepit slicer 41 configured togenerate the prepit clock PCLK by subjecting the prepit signal PS towaveform shaping. Note that the prepit decoder 27 a generates physicaladdress information of the optical disk 11 in accordance with the prepitsignal PS and the wobble clock WCLK. The physical address information ofthe optical disk 11 is supplied to the modulator 24 a. The physicaladdress information of the optical disk 11 is utilized for generating arecord start signal SS to be supplied to the timing controller 58 a.

[0037] The decision circuit 33 a includes an address register 42 ahaving a clock input terminal CK connected to the prepit decoder 27 aand an input side connected to the modulator 24 a, a dividing correctioncircuit 4 a connected to the address register 42 a, and a dividingcorrection register 49 a having an enable terminal EN connected to thetiming controller 58 a and an input side connected to the dividingcorrection circuit 4 a. The address register 42 a latches the addressinformation AD of the modulation data MD in synchronization with theprepit clock PCLK. The dividing correction circuit 4 a generates adividing correction signal CS based on latched address information AD.The dividing correction register 49 a latches the dividing correctionsignal CS when the timing signal TS is effective.

[0038] The dividing correction circuit 4 a includes a decoder 43 aconnected to the address register 42 a, and a window circuit 44 aconnected between the decoder 43 a and the dividing correction register49 a. The decoder 43 a generates the phase characteristic PC from thelatched address information AD. The window circuit 44 a generates thedividing correction signal CS by comparing the phase characteristic PCto a window value. Moreover, the window circuit 44 a has a positivewindow value and a negative window value. The window circuit 44 adetermines to which one of three patterns the phase characteristic PCcorresponds. Specifically, the window circuit 44 a determines whetherthe phase characteristic PC is a value larger than the positive windowvalue or a value smaller than the negative window value or a valuebetween the negative window value and the positive window value,inclusive. When the phase characteristic PC supplied from the decoder 43a is a value larger than the positive window value, the window circuit44 a supplies “+1” to the dividing correction register 49 a. On theother hand, when the phase characteristic PC is a value smaller than thenegative window value, the window circuit 44 a supplies “−1” to thedividing correction register 49 a. When the phase characteristic PC is avalue between the negative window value and the positive window value,inclusive, the window circuit 44 a supplies “0” to the dividingcorrection register 49 a.

[0039] Furthermore, the record clock generator 30 a includes a dividingsetting register 50 configured to receive a command COM, an adder 51having one input connected to the dividing setting register 50 and theother input connected to the dividing correction register 49 a, and aPLL 62 connected to the adder 51. The command COM generated by thesystem controller 31 a shown in FIG. 4 is supplied to the dividingsetting register 50. The dividing setting register 50 generates areference dividing signal in accordance with the command COM. The adder51 generates a dividing control signal DS by adding up the referencedividing signal and the dividing correction signal CS. The PLL 62generates the record clock RCLK based on the dividing control signal DS.

[0040] The PLL 62 includes a voltage controlled oscillator (VCO) 53configured to generate an oscillation clock SVCO by oscillating at afrequency corresponding to a control voltage CV, a programmable counter52 configured to change a dividing ratio by use of the dividing controlsignal DS, and to divide the oscillation clock SVCO, a first divider 55configured to generate a dividing clock DCLK by dividing any one of thereference clock CLK1 and the wobble clock WCLK, a phase comparator 54configured to generate the control voltage CV in accordance with a phasedifference between the divided oscillation clock SVCO and the dividingclock DCLK, a loop filter 61 configured to extract a low frequencycomponent of the control voltage CV, and to supply the component to theVCO 53, and a second divider 56 configured to generate the record clockRCLK by dividing the oscillation clock SVCO. The dividing ratio of theprogrammable counter 52 is increased when the dividing correction signalCS from the window circuit 44 a is “+1”. On the other hand, the dividingratio of the programmable counter 52 is decreased when the dividingcorrection signal CS is “−1”.

[0041] The signal processor 3 a and the servo controller 16, which areshown in FIG. 4, supply a disk discrimination signal for discriminatingthe type of the optical disk 11 to the system controller 31 a. Based onthe disk discrimination signal, the system controller 31 a determinesthe type of the optical disk 11. In accordance with the type of opticaldisk 11, the system controller 31 a supplies the command COM to thedividing setting register 50 and determines a reference frequency of therecord clock RCLK.

[0042] Furthermore, the reproducing synchronization signal RP suppliedfrom the demodulator 18 shown in FIG. 4 is transmitted to a switchcircuit 65. A rotation frequency signal FG from the disk motor 71 issupplied to the disk motor controller 29, and the disk motor 71 iscontrolled so that the rotation frequency signal FG has a constantperiod. The switch circuit 65 switches between the wobble clock WCLK,the rotation frequency signal FG, and the reproducing synchronizationsignal RP in accordance with an operation mode signal from the systemcontroller 31 a. Any one of the wobble clock WCLK, the rotationfrequency signal FG, and the reproducing synchronization signal RP,which is selected by the switch circuit 65, is supplied to the diskmotor controller 29. The disk motor controller 29 compares the signalselected by the switch circuit 65 to the reference clock CLK1 andcontrols a disk motor driver 28 in accordance with the comparisonresult. Note that two methods can be used for controlling the disk motor71, a constant angular velocity (CAV) method and a constant linearvelocity (CLV) method. An optical disk drive for a DVD and the likegenerally adopts the CLV method in recording and the CAV method inreproducing.

[0043] In reproducing data, the information signal RF generated by theRF amplifier 15 is transmitted to a host computer 75 via the demodulator18, an error correction circuit 19, a correction RAM 20, a data buffer21, and a data buffer RAM 22. On the other hand, in recording data, datafrom the host computer 75 is supplied to the modulator 24 a via the databuffer 21, the data buffer RAM 22 and a parity generator 23. Themodulator 24 a modulates the record data RD to which parities are added.

[0044] The error correction circuit 19, the data buffer 21, and theparity generator 23 operate in synchronization with a clock generated bya signal process PLL 32. The modulator 24 a operates in synchronizationwith the record clock RCLK generated by the record clock generator 30 a.The record clock RCLK is generated by the record clock generator 30 abased on the wobble clock WCLK. The servo controller 16 drives a feedmotor 14 and tracking and focus actuators inside the pickup 12 via adriver 17 based on the error signal ES.

[0045] The record data RD as shown in FIG. 6A has record syncs at theheads of each sync frame. The RF amplifier 15 generates the wobblesignal WS and prepit signals PS1, PS2, . . . as shown in FIG. 6B. Theprepit signals PS1 to PS3, PS6 and PS7 correspond to prepits of a tracktraced by the pickup 12 and occur at peak positions of a waveform of thewobble signal WS. The prepit signals PS4 and PS5 occur at positionscorresponding with prepits of a track adjacent to the track traced bythe pickup 12. When the prepits of the adjacent track and the prepits ofthe traced track overlap with each other and are canceled out byinterfering with each other, the standards prescribe that the prepits ofthe traced track are shifted by one frame to the head of a subsequentframe. As to the prepits of the optical disk 11, a maximum of threeprepits are inscribed at peak positions of three periods of a wobble ina frame head in accordance with the DVD standards. In the case of a DVD,the period of the wobble, when converted into channel bits of data, is aperiod of 186 channel bits. Since the standards prescribe that arecording/reproducing frequency of the channel bits is to be 26.16 MHz,the wobble frequency is 26.16 MHz/186=140.6 kHz. The prepits on theoptical disk 11 are inscribed so as to form one code by a unit of anerror correction coding (ECC) block on a DVD data format. A set ofprepit data includes three or two prepit signals PS. Moreover, one setof the prepit data is recorded for every two frames.

[0046] Moreover, the standard prescribes that recording positions of therecord syncs inserted into the new data and the positions of prepits onthe optical disk 11 must coincide with each other. As shown in FIG. 7A,a signal section of the record sync, when converted into a channel bit,includes 14T at the low level and 4T at the high level or 14T at thehigh level and 4T at the low level. Furthermore, the standard requiresthat center positions of 14T of the record sync and the positions of theprepits coincide with each other. As shown in FIG. 7B, a phase of theprepit signal PS is not modulated, unlike the wobble signal WS. Whenconverted into channel bits, the oscillation of the wobble signal WS dueto this wobble modulation corresponds to ±16 to 20 channel bits.Accordingly, the controller 1 a allows the center of 14T of the recordsync of the modulation data MD shown in FIG. 7A and the timing of theprepit signal PS shown in FIG. 7B to coincide with each other.

[0047] Next, an operation of the controller 1 a according to the firstembodiment of the present invention will be described by using FIGS. 4to 10.

[0048] (A) As shown in FIG. 8A, the RF amplifier 15 shown in FIG. 4generates the wobble signal WS similar to the meandering of the wobble.Assuming that signals obtained from the A to D sections of the opticaldetector inside the pickup 12 are signals A to D, respectively, thewobble signal WS is generated by a matrix operation of (A+B) - (C+D). Asshown in FIGS. 8A and 8B, the numbers of occurring prepits differ fromeach other depending on frames. The wobble signal WS generated by the RFamplifier 15 is supplied to the wobble PLL 26 a. The wobble PLL 26 abinarizes the wobble signal WS and, thereafter, multiplies the binarizedsignal. Thus, the wobble clock WCLK is generated. The wobble clock WCLKis supplied to the modulator 24 a and the record clock generator 30 a.Furthermore, the wobble clock WCLK is supplied to the wobble counter 57a inside the modulator 24 a shown in FIG. 5.

[0049] (B) Next, the wobble counter 57 a generates the sectorsynchronization signal SY by counting the wobble clock WCLK. The sectorsynchronization signal SY is supplied to the timing controller 58 ashown in FIG. 5. The record start signal SS is also supplied to thetiming controller 58 a, in addition to the sector synchronization signalSY. When a recording operation is started, the timing signal TS isgenerated. When the timing signal TS is generated, the encode addresscounter 40 b starts counting the record clock RCLK.

[0050] (C) The encode address counter 40 a counts the record clock RCLKand generates the modulation control signal MC and the addressinformation AD of the modulation data MD. The modulation data generator59 a generates a bit clock in accordance with the modulation controlsignal MC and performs 8-16 modulation in synchronization with therecord clock RCLK. The address information AD of the modulation data MD,which is generated by the encode address counter 40 a, is supplied tothe address register 42 a. Moreover, the prepit signal PS is subjectedto waveform shaping by the prepit slicer 41 inside the prepit decoder 27a and becomes the prepit clock PCLK. The prepit clock PCLK is suppliedto the address register 42 a inside the decision circuit 33 a.

[0051] (D) In synchronization with the prepit clock PCLK, the addressregister 42 a latches the address information AD generated by the encodeaddress counter 40 a. As a result, a positional relationship between theaddress value of the address information AD and the prepit signal PS canbe obtained, as shown in FIG. 8C. The latch signal LS generated by theaddress register 42 a is supplied to the decoder 43 a shown in FIG. 5.The decoder 43 a generates the phase characteristic PC on the basis of apoint with which the modulation data MD should be synchronous inaccordance with the standards. Specifically, based on a positionalrelationship between the prepit signal PS and the record sync of themodulation data MD, the decoder 43 a obtains an error between the prepitand the address value of the center position of 14T of the record sync.Furthermore, as shown in FIG. 9, the decoder 43 a generates the phasecharacteristic PC based on an error between the prepit and the addressvalue of the center position of 14T of the record sync. The phasecharacteristic PC generated by the decoder 43 a is supplied to thewindow circuit 44 a.

[0052] (E) The window circuit 44 a compares the phase characteristic PCgenerated by the decoder 43 a to the window value at a specific timing.Here, it is assumed that the positive and negative window values of thewindow circuit 44 a are set to “+4” and “−4”, respectively. As shown inFIG. 9, in the phase characteristic PC, only the characteristic duringone wobble has a linear region. The window circuit 44 a compares thephase characteristic PC to the window value in synchronization with aphase decision timing pulse TP shown in FIG. 8D. The phase decisiontiming pulse TP is supplied, for example, from the system controller 31a. In the window circuit 44 a, the phase characteristic PC is “+2” attime t1, which is between the negative window value and the positivewindow value, inclusive. Therefore, as shown in FIG. 8E, “0” isgenerated as the dividing correction signal CS. The phase characteristicPC is “+3” at time t2, which is between the negative window value andthe positive window value, inclusive. Therefore a “0” is generated. Thephase characteristic PC is “+5” at time t3, which is larger than thepositive window value, and therefore the window circuit 44 a generates“+1”. The phase characteristic PC is “+1” at time t4, which is betweenthe negative window value and the positive window value inclusive, andtherefore the window circuit 44 a generates “0”. The phasecharacteristic PC is “0” at time t5, which is between the negativewindow value and the positive window value, inclusive, and therefore thewindow circuit 44 a generates “0”. The phase characteristic PC is “−4”at time t6, which is between the negative window value and the positivewindow value inclusive, and therefore the window circuit 44 a generates“0”. The phase characteristic PC is “−8” at time t7, which is smallerthan the negative window value, and therefore the window circuit 44 agenerates “−1”. The phase characteristic PC is “-5” at time t8, which issmaller than the negative window value, and therefore the window circuit44 a generates “−1”. The dividing correction signals CS generated by thewindow circuit 44 a are supplied to the dividing correction register 49a.

[0053] (F) The dividing correction register 49 a latches the dividingcorrection signals CS generated by the window circuit 44 a and suppliesthe dividing correction signals CS to the adder 51. The adder 51 adds upthe dividing correction signals CS from the dividing correction register49 a and the reference dividing signal from the dividing settingregister 50. The dividing correction signals CS and the referencedividing signal, which are added up by the adder 51, are supplied to theprogrammable counter 52 of the PLL 62. When the output of the windowcircuit 44 a is “−1”, an input signal from the optical disk 11 isdelayed in comparison with the modulation control signal MC generated bythe encode address counter 40 a. When the output of the window circuit44 a is “+1”, the input signal from the optical disk 11 is ahead of themodulation control signal MC generated by the encode address counter 40a. The adder 51 supplies the dividing control signal DS to theprogrammable counter 52. The programmable counter 52 controls anoscillation frequency of the VCO 53. The oscillation clock SVCOgenerated by the VCO 53 is divided by the second divider 56 and issupplied as the record clock RCLK to the encode address counter 40 a.

[0054] As described above, according to the first embodiment, in thecase of recording new data on the basis of previously recorded data,phases of the modulation data MD and the wobble signal WS are detectedso as to conform to the prepit signal PS and the wobble signal WS, andthe frequency of the record clock RCLK is modulated in minute scales. Bymodulating the frequency of the record clock RCLK, even when therecording starting position is largely deviated from its original linkposition, an original recording state in accordance with the establishedstandards during recording. Moreover, in the case of recording new dataon the basis of the wobble signal WS, the modulation data MD can berecorded in accordance with the established standards based on theprepit signal PS and the wobble signal WS in the process of therecording operation. As a result, in any of the cases of starting theadditional write in synchronization with the wobble signal WS and ofstarting the additional write in conjunction with the previouslyrecorded data, recording in accordance with the established standardscan be performed on the optical disk 11 while executing the recordingoperation.

[0055] As shown in FIG. 10, for example, the modulator 24 a, the prepitdecoder 27 a, wobble PLL 26 a, the decision circuit 33 a, and the recordclock generator 30 a can be monolithically integrated on a semiconductorchip 95 a and a semiconductor integrated circuit 91 a can be formed. Inthe example shown in FIG. 10, the semiconductor integrated circuit 91 afurther includes the servo controller 16, the signal processor 3 a, thedisk motor controller 29, and bonding pads 81 a to 81 k.

[0056] The bonding pad 81 a is an internal terminal for transmitting theerror signal ES supplied from the RF amplifier 15 to the servocontroller 16. The bonding pad 81 b is an internal terminal fortransmitting the information signal RF supplied from the RF amplifier 15to the demodulator 18. Similarly, the bonding pad 81 c is electricallyconnected to the modulator 24 a. The bonding pad 81 d is electricallyconnected to the prepit decoder 27 a. The bonding pad 81 e iselectrically connected to the wobble PLL 26 a. The bonding pad 81 f iselectrically connected to the switch circuit 65. The bonding pad 81 g iselectrically connected to the disk motor controller 29. The bonding pad81 i is electrically connected to the data buffer 21. The bonding pad 81j is electrically connected to the each block shown in FIG. 10. Thebonding pad 81 k is electrically connected to the disk motor controller29 and the signal process PLL 32.

[0057] More specifically, the bonding pads 81 a to 81 k are connectedto, for example, a plurality of high impurity concentration regions(source region/drain region) formed in and at the surfaces of activearea assigned to the surface of the semiconductor chip 95 a, wheredonors or acceptors are doped with a concentration of approximately1×10¹⁸ to 1×10²¹ cm⁻³. A plurality of electrode layers made from a metalsuch as aluminum (Al) or an aluminum alloy (Al—Si, Al—Cu—Si) are formedso as to implement ohmic contacts with the plurality of high impurityconcentration regions. On the top surface of such a plurality ofelectrode layers, a passivation film such as a silicon oxide film(SiO₂), a phosphosilicate glass (PSG) film, a boro-phosphosilicate glass(BPSG) film, a silicon nitride film (Si₃N₄), or a polyimide film, isdeposited.

[0058] A plurality of openings (contact holes) are delineated in aportion of the passivation film so as to expose a plurality of electrodelayers, implementing the bonding pads 81 a to 81 k. Alternatively, thebonding pads 81 a to 81 k may be formed as other metal patternsconnected to a plurality of electrode layers by using metal wiring. Inaddition, it is possible to form bonding pads 81 a to 81 k on thepolysilicon gate electrodes using a metal film such as aluminum (Al) oran aluminum alloy (Al—Si, Al—Cu—Si). Alternatively, a plurality of otherbonding pads may be connected, via a plurality of signal lines such asgate wirings, to the polysilicon gate electrodes. Instead ofpolysilicon, gate electrodes made of a refractory metal such as tungsten(W), titanium (Ti), or molybdenum (Mo), a silicide (i.e. WSi₂, TiSi₂,MoSi₂), or a polycide containing any of these suicides can be used.

[0059] As shown in FIG. 11, the semiconductor integrated circuit 91 ashown in FIG. 10 is covered by a mold resin 98, and a packagedsemiconductor integrated circuit 92 is formed. Furthermore, as shown inFIG. 11, the packaged semiconductor integrated circuit 92 is implementedon printed board 96.

[0060] (Second Embodiment)

[0061] As shown in FIG. 12, an optical disk drive according to a secondembodiment of the present invention is different from the optical diskdrive shown in FIG. 4 in that the modulator 24 b further generates asector pulse SP, which is a pulse of a sector interval of the opticaldisk 11. A decision circuit 33 b determines whether or not recording isperformed in accordance with the standards by use of the addressinformation AD, the prepit clock PCLK, and the sector pulse SP. As shownin FIG. 13, the sector pulse SP is generated when the wobble counter 57b of the modulator 24 b counts the wobble clock WCLK.

[0062] As shown in FIG. 13, the decision circuit 33 b includes anaddress register 42 a having a clock input terminal CK connected to theprepit decoder 27 a and an input side connected to the modulator 24 a, adividing correction circuit 4 a connected to the address register 42 a,and a dividing correction register 49 a having a enable terminal ENconnected to the timing controller 58 a and an input side connected tothe dividing correction circuit 4 a. The first address register 42 blatches the address information AD in synchronization with the prepitclock PCLK and generates a first latch signal LS1. The second addressregister 45 latches the address information AD of the modulation data MDin synchronization with the sector pulse SP and generates a second latchsignal LS2. The dividing correction circuit 4 b generates dividingcorrection signal CS based on the first and second latch signals LS1 andLS2. The dividing correction register 49 b latches the dividingcorrection signal CS when the timing signal TS is effective.

[0063] The dividing correction circuit includes a first decoder 43 bconnected to the first address register 42 b, a second decoder 46connected to the second address register 45, a first window circuit 44 bconnected to the first decoder 43 b, a second window circuit 47connected to the second decoder 46, and a window decision circuit 48connected to the first window circuit 44 b and the second window circuit47. The first decoder 43 b generates a first phase characteristic PC1 asthe phase characteristic from the first latch signal LS1. The seconddecoder 46 generates a second phase characteristic PC2 as the phasecharacteristic from the second latch signal LS2. The first windowcircuit 44 b compares the first phase characteristic PC1 to a windowvalue and generates a first dividing correction signal CS1. The secondwindow circuit 47 compares the second phase characteristic PC2 to awindow value and generates a second dividing correction signal CS2. Thewindow decision circuit 48 selects either one of the first and seconddividing correction signals CS1 and CS2. Specifically, the windowdecision circuit 48 normally selects the second dividing correctionsignal CS2 and, when the second dividing correction signal CS2 is “0”,selects the first dividing correction signal CS1.

[0064] As shown in FIG. 14A, between the previously recorded data on theoptical disk 11 and data to be newly recorded, a link position isdetermined by the standards. Specifically, in the case of recording newdata on the previously recorded data, the link position is determined bythe standards to be at 16th byte of a first sector. Recording accuracyis required to be the±1 byte on the basis of the 16th byte of the firstsector. The controller 1 b detects an initial point of the sector bycounting the wobble signal WS shown in FIG. 14B and determines timingfor generating the modulation data MD. Note that one ECC block of therecord data RD includes 16 sectors.

[0065] Next, an operation of the controller 1 b according to the secondembodiment of the present invention will be described by use of FIGS. 12to 14B. Repeated descriptions for the same operations according to thesecond embodiment which are the same as the first embodiment of thepresent invention are omitted.

[0066] (A) The RF amplifier 15 generates the wobble signal WS and theprepit signal PS as shown in FIGS. 15A and 15B, respectively. The wobblecounter 57 b shown in FIG. 13 generates the sector pulse SP by countingthe wobble clock WCLK. The address information AD of the modulation dataMD is supplied to the first and second address registers 42 b and 45. Asshown in FIG. 15C, the first address register 42 b latches the addressvalue AD by use of the prepit clock PCLK. On the other hand, as shown inFIG. 15D, the second address register 45 latches the address value AD byuse of the sector pulse SP. The second latch signal LS2 will be a valueobtained by expressing one sector by byte, as shown in FIG. 16A. Onesector is 2418 bytes as expressed in bytes.

[0067] (B) Next, the first and second decoders 43 b and 46 generate thefirst and second phase characteristics PC1 and PC2 from the first andsecond latch signals LS1 and LS2, respectively. The first and secondphase characteristics PC1 and PC2 are supplied to the first and secondwindow circuits 44 b and 47, respectively. Here, it is assumed that thepositive and negative window values of the first window circuit 44 b areset to “+4” and “−4”, respectively. Moreover, it is assumed that thepositive and negative window values of the second window circuit 47 areset to “+5” and “−5”, respectively. In the period of times t1 to t4, asshown in FIG. 15D, the phase characteristic PC generated by the seconddecoder 46 is “+1”, which is between the negative window value and thepositive window value of the second window circuit 47, inclusive.Therefore, the second window circuit 47 generates “0”. Since the seconddividing correction signal CS2 is “0”, the window decision circuit 48latches the first dividing correction signal CS1. As a result, thewindow decision circuit 48 outputs “+1” at time t3.

[0068] (C) In the period of times t5 to t8, the second phasecharacteristic PC2 shown in FIG. 15D is “−9”, which is smaller than thenegative window value of the second window circuit 47. The second windowcircuit 47 generates “+1” in the period of times t5 to t8. In the periodof times t5 to t8, the window decision circuit 48 ignores the firstdividing correction signal CS1 since the second dividing correctionsignal CS2 is not “0”. As a result, as shown in FIG. 15F, the windowdecision circuit 48 outputs “−1” as the dividing correction signal CS inthe period of times t5 to t8. The values −1, “0” and “+1” generated bythe window decision circuit 48 are latched by the dividing correctionregister 49 b. The record clock generator 30 b generates the recordclock RCLK based on the dividing correction signal CS generated by thedividing correction register 49 b.

[0069] As described above, according to the second embodiment, first, byadjusting positions of the record sync and the prepits by sector, thepositions of the record sync and the prepits are allowed to roughlycoincide with each other. Thereafter, fine adjustment of the positionalrelationship between the record sync and the prepits is performed.Therefore, even if the link position drastically deviates from thestandards, new data can be recorded in original data positions, asprescribed by the standards.

[0070] As shown in FIG. 17, for example, the modulator 24 b, the prepitdecoder 27 b, wobble PLL 26 b, the decision circuit 33 b, and the recordclock generator 30 b can be monolithically integrated on a semiconductorchip 95 b and a semiconductor integrated circuit 91 b can be formed. Inthe example shown in FIG. 17, the semiconductor integrated circuit 91 bfurther includes the servo controller 16, the signal processor 3 b, thedisk motor controller 29, and bonding pads 83 a to 83 k.

[0071] (Other Embodiments)

[0072] Various modifications will become possible for those skilled inthe art after receiving the teachings of the present disclosure withoutdeparting from the scope thereof.

[0073] In the first embodiment, the description was given that thedecision circuit 33 a determines only the phases of the record data RDand the prepit signal PS. In the second embodiment, the description wasgiven that the decision circuit 33 b determines the phases of the recorddata RD and each of the prepit signal PS and the sector interval.However, as shown in FIG. 18, the decision circuit 33 c may determineonly the phases of the record data RD and the sector interval. That is,the decision circuit 33 c may includes an address register 42 c having aclock input terminal CK connected to the wobble counter 57 c and aninput side connected to the encode address counter 40 c, a decoder 43 cconnected to the address register 42 c, a window circuit 44 c connectedto the decoder 43 c, a dividing correction register 49 c having anenable terminal EN connected to the timing controller 58 c and an inputside connected to the window circuit 44 c. Moreover, in a DVD+R/RW,although there is no prepit, the record data RD and the modulation dataMD are recorded by a sector interval similarly to a DVD−R/RW. Therefore,it is needless to say that the present invention can be applied to aDVD+R/RW drive.

[0074] In each of the first and second embodiments, description wasgiven of an example in which the RF amplifier 15, the laser driver 25and the system controller 31 a or 31 b are not integrated on the singlesemiconductor chip 95 a or 95 b. However, it is possible to have aconfiguration of a single chip system LSI by further integrating the RFamplifier 15, the laser driver 25 and the system controller 31 a or 31 bon the single semiconductor chip 95 a or 95 b. Moreover, the data bufferRAM 22 of the semiconductor integrated circuits (in a chip state) 91 aand 91 b according to the first and second embodiments, respectively,can also be an external component without being integrated on the singlesemiconductor chips 95 a and 95 b.

[0075] In the first and second embodiments, the description was given ofthe case where the system controllers 31 a and 31 b generate the phasedecision timing pulse TP used in window processing, respectively.However, a phase decision timing pulse generator using the prepit signalPS as its input signal may be additionally included in the prepitdecoders 27 a and 27 b.

What is claimed is:
 1. A controller for an optical disk drivecomprising: a modulator configured to modulate record data to berecorded on an optical disk based on a record clock which is a referenceclock for recording, and to generate modulation data and addressinformation of the modulation data; a prepit decoder configured togenerate a prepit clock from a prepit signal detected from the opticaldisk; and a decision circuit configured to determine whether recordingin accordance with a standard is performed, from a phase characteristicbased on the address information and the prepit clock, and to control afrequency of the record clock.
 2. The controller of claim 1, wherein theprepit decoder comprises a prepit slicer configured to generate theprepit clock by subjecting the prepit signal to waveform shaping.
 3. Thecontroller of claim 1, further comprising: a wobble PLL configured togenerate a wobble clock based on a wobble signal detected from theoptical disk; and a record clock generator configured to generate therecord clock.
 4. The controller of claim 3, wherein the modulatorcomprises: a wobble counter configured to generate a sectorsynchronization signal by counting the wobble clock; a timing controllerconfigured to generate a timing signal in synchronization with eitherone of the sector synchronization signal and a reproducingsynchronization signal obtained from previously recorded data on theoptical disk; an encode address counter configured to generate amodulation control signal and the address information by counting therecord clock when the timing signal is effective; and a modulation datagenerator configured to modulate the record data based on the modulationcontrol signal.
 5. The controller of claim 4, wherein the wobble counterfurther generates a sector pulse by an interval of a sector of theoptical disk.
 6. The controller of claim 4, wherein the decision circuitcomprises: an address register configured to latch the addressinformation in synchronization with the prepit clock; a dividingcorrection circuit configured to generates a dividing correction signalbased on latched address information; and a dividing correction registerconfigured to latch the dividing correction signal when the timingsignal is effective.
 7. The controller of claim 6, wherein the dividingcorrection circuit comprises: a decoder configured to generate the phasecharacteristic from the latched address information; and a windowcircuit configured to generate the dividing correction signal bycomparing the phase characteristic to a window value.
 8. The controllerof claim 7, wherein the window circuit has a positive window value and anegative window value as the window value
 9. The controller of claim 6,wherein the record clock generator comprises: a dividing settingregister configured to generate a reference dividing signal inaccordance with a command; an adder configured to generate a dividingcontrol signal by adding the reference dividing signal and the dividingcorrection signal; and a PLL configured to generate the record clockbased on the dividing control signal.
 10. The controller of claim 9,wherein the PLL comprises: a VCO configured to generate an oscillationclock by oscillating at a frequency corresponding to a control voltage;a programmable counter configured to change a dividing ratio by applyingthe dividing control signal, and to divide the oscillation clock; afirst divider configured to generate a dividing clock by dividing eitherof a reference clock and the wobble clock; a phase comparator configuredto generate the control voltage in accordance with a phase differencebetween the divided oscillation clock and the dividing clock; a loopfilter configured to extract a low frequency component of the controlvoltage, and to supply the low frequency component to the VCO; and asecond divider configured to generate the record clock by dividing theoscillation clock.
 11. The controller of claim 5, wherein the decisioncircuit comprises: an address register configured to latch the addressinformation in synchronization with the sector pulse; a dividingcorrection circuit configured to generates a dividing correction signalbased on latched address information; and a dividing correction registerconfigured to latch the dividing correction signal when the timingsignal is effective.
 12. The controller of claim 11, wherein thedividing correction circuit comprises: a decoder configured to generatethe phase characteristic from the latched address information; and awindow circuit configured to generate the dividing correction signal bycomparing the phase characteristic to a window value.
 13. The controllerof claim 12, wherein the window circuit has a positive window value anda negative window value as the window value.
 14. The controller of claim11, wherein the record clock generator comprises: a dividing settingregister configured to generate a reference dividing signal inaccordance with a command; an adder configured to generate a dividingcontrol signal by adding the reference dividing signal and the dividingcorrection signal; and a PLL configured to generate the record clockbased on the dividing control signal.
 15. The controller of claim 14,wherein the PLL comprises: a VCO configured to generate an oscillationclock by oscillating at a frequency corresponding to a control voltage;a programmable counter configured to change a dividing ratio by use ofthe dividing control signal, and to divide the oscillation clock; afirst divider configured to generate a dividing clock by dividing eithera reference clock and the wobble clock; a phase comparator configured togenerate the control voltage in accordance with a phase differencebetween the divided oscillation clock and the dividing clock; a loopfilter configured to extract a low frequency component of the controlvoltage, and to supply the low frequency component to the VCO; and asecond divider configured to generate the record clock by dividing theoscillation clock.
 16. The controller of claim 5, wherein the decisioncircuit comprises: a first address register configured to latch theaddress information in synchronization with the prepit clock, and togenerate a first latch signal; a second address register configured tolatch the address information in synchronization with the sector pulseand to generate a second latch signal; a dividing correction circuitconfigured to generate a dividing correction signal based on the firstand second latch signals; and a dividing correction register configuredto latch the dividing correction signal when the timing signal iseffective.
 17. The controller of claim 16, wherein the dividingcorrection circuit comprises: a first decoder configured to generate afirst phase characteristic as the phase characteristic from the firstlatch signal; a second decoder configured to generate a second phasecharacteristic as the phase characteristic from the second latch signal;a first window circuit configured to compare the first phasecharacteristic to a window value, and to generate a first dividingcorrection signal; a second window circuit configured to compare thesecond phase characteristic to a window value, and to generate a seconddividing correction signal; and a window decision circuit configured toselect either one of the first and second dividing correction signals.18. The controller of claim 17, wherein the record clock generatorcomprises: a dividing setting register configured to generate areference dividing signal in accordance with a command; an adderconfigured to generate a dividing control signal by adding up thereference dividing signal and the dividing correction signal; and a PLLconfigured to generate the record clock based on the dividing controlsignal.
 19. A semiconductor integrated circuit comprising: a modulatorintegrated on a semiconductor chip and configured to modulate a recorddata to be recorded on a optical disk based on a record clock that is areference clock for recording, and to generate a modulation data and anaddress information of the modulation data; a prepit decoder integratedon the semiconductor chip and configured to generate a prepit clock froma prepit signal detected from the optical disk; and a decision circuitintegrated on the semiconductor chip and configured to determine whetheror not recording in accordance with a standard is performed, from phasecharacteristic based on the address information and the prepit clock,and to control a frequency of the record clock.
 20. An optical diskdrive comprising: a pickup configured to read light reflected from anoptical disk, the reflected light generated by irradiating a laser beamon the optical disk, and to generate a prepit signal and a wobblesignal; a controller configured to determine whether recording inaccordance with an established standards is performed, from phasecharacteristic based on the prepit signal and the wobble signal, and tomodulate record data to be recorded on the optical disk; and a signalprocessor configured to supply the record data to the controller.